A) Field of the Invention
The present invention relates to an inspection method for a semiconductor memory, and more particularly to an inspection method for a semiconductor memory using ferroelectric material.
B) Description of the Related Art
Because of recent spread of portable apparatus, demands for energy savings and reduction in wastes, there are high demands for nonvolatile memories capable of storing data even if a power supply is stopped. Semiconductor memories using ferroelectric capacitors (FeRAM) are nonvolatile memories capable of operating at a low voltage and rewriting data a number of times, and are widely used in integrated circuits incorporating logic circuits, and in other integrated circuits.
FIG. 6A is a schematic cross sectional view showing the structure of a ferroelectric capacitor. A ferroelectric layer 105 is sandwiched between a lower electrode 101 and an upper electrode 102 to constitute a ferroelectric capacitor. For example, the lower electrode is connected to a plate line PL and the upper electrode is connected to a bit line BL via a switching transistor.
As a pulse voltage of a positive polarity is applied to the upper electrode 102 relative to the lower electrode 101, an upward first polarized state S1 is left in the ferroelectric layer 105. As a pulse voltage of an opposite polarity is applied, a downward second polarized state S2 is left in the ferroelectric layer 105.
FIG. 6B is a graph showing the hysteresis characteristics of ferroelectric material. The abscissa represents a voltage applied to the lower electrode 101 with the upper electrode as a reference. The ordinate represents a polarization (charge) P in the ferroelectric layer. As an applied voltage is scanned, state transition with hysteresis characteristics occurs as indicated by arrows. A voltage at the cross point between the hysteresis curve and a voltage axis is a coercive voltage Vc. This will be described in more detail. It is assumed that the ferroelectric layer is in the polarized state S1, and that a pulse Vp of a positive polarity is applied to the lower electrode 101.
As show in FIG. 6C, as the voltage applied to the lower electrode rises, state transition occurs in the ferroelectric layer as indicated by an arrow and the upward polarization reduces. As the voltage rises further, downward polarization increases. A state T1 is established at a peak voltage V1. During this change, positive charges flow into the lower electrode, and positive charges P are drained out from the upper electrode 102 to the bit line BL. As the applied voltage is lowered, the state T1 in the ferroelectric layer changes to a state S2. During this change, negative charges Pa are drained out from the upper electrode 102 to the bit line BL.
FIG. 6D illustrates state transition while a pulse voltage Vp of the positive polarity is applied to the lower electrode of the ferroelectric capacitor in the polarized state S2. As the pulse voltage rises, state transition occurs in the ferroelectric capacitor from S2 to T1 and positive charges U are drained out from the upper electrode 102 to the bit line BL. As the pulse voltage falls, state transition occurs in the ferroelectric capacitor from T1 to S2 and negative charges Ua are drained out from the upper electrode 102 to the bit line BL.
FIG. 6E illustrates state transition when a pulse voltage Vn of the negative polarity is applied to the lower electrode of the ferroelectric capacitor, which has been in the polarized state S2. As the pulse voltage Vn of the negative polarity rises, state transition occurs in the ferroelectric capacitor from S2 to T2 and negative charges N are drained out from the upper electrode 102 to the bit line BL. As the pulse voltage Vn of the negative polarity falls, state transition occurs in the ferroelectric capacitor from T2 to S1 and positive charges Na are drained out from the upper electrode 102 to the bit line BL.
FIG. 6F illustrates state transition when a pulse voltage Vn of the negative polarity is applied to the lower electrode of the ferroelectric capacitor which has been in the polarized state S1. As the pulse voltage of the negative polarity rises, state transition occurs in the ferroelectric capacitor from S1 to T2 and negative charges D are drained out from the upper electrode 102 to the bit line BL. As the pulse voltage of the negative polarity falls, state transition occurs in the ferroelectric capacitor from T2 to S1 and positive charges Da are drained out from the upper electrode 102 to the bit line BL.
A ferroelectric capacitor demonstrates a phenomenon called imprint as shown in FIG. 7A. In FIG. 7A, the abscissa and ordinate represent a lower electrode voltage and polarization similar to FIG. 6B. There is a tendency that the hysteresis characteristics change from H0 to H1 as the polarized state S1 is held. As the reversed polarized state S2 is held, there is a tendency that the hysteresis characteristics change from H0 to H2 opposite to H1.
As shown in FIG. 7B, as the polarized state S1 is held and the hysteresis characteristics are imprinted from H0 to H1, an accumulated polarization amount is reduced by a polarization amount ΔP1 when S1 of the opposite polarity is written thereafter.
As shown in FIG. 7C, as the polarized state S2 is held and the hysteresis characteristics are imprinted from H0 to H2, an accumulated polarization amount is reduced by a polarization amount ΔP2 when S1 of the opposite polarity is written thereafter. If the polarization amount reduces and it becomes impossible to read, the function of a memory device is lost.
FIG. 8A shows an example of the structure of a memory cell of FeRAM of two transistors and two capacitors (2T/2C) type. One FeRAM cell includes two ferroelectric capacitors Cx and Cy and two switching transistors Tx and Ty whose drain electrodes are connected to the upper electrodes of the ferroelectric capacitors. The source electrodes of the two switching transistors Tx and Ty are connected to bit lines BL and /BL, the gate electrodes are connected in common to a word line WL, and the lower electrodes of the ferroelectric capacitors Cx and Cy are connected in common to a plate line PL. A sense amplifier SA is connected between the bit lines BL and /BL.
Information of opposite polarities is stored in the ferroelectric capacitors Cx and Cy. For example, when “1” is to be stored, information “1” is stored in the ferroelectric capacitor Cx and information “0” is stored in the ferroelectric capacitor Cy. When data is read, the sense amplifier SA detects a voltage difference between the bit lines BL and /BL.
A 1T/1C structure is also used, which constitutes one memory cell by one transistor and one capacitor. In this case, for example, a combination of a right transistor and a right ferroelectric capacitor is used as a memory cell, and a reference cell is used in place of a combination of a left transistor and a left ferroelectric capacitor. Although a charge amount capable of being detected is reduced to a half, there is no essential difference. Therefore, in the following the 2T/2C structure will be described by way of example.
FIG. 8B illustrates a procedure of inspecting FeRAM. FIG. 8C is a diagram showing pulse voltage trains applied to two ferroelectric capacitors Cx and Cy of one FeRAM with indication of charge outputs drained to the bit lines during execution of the procedure shown in FIG. 8B. The pulse voltage is applied to the lower electrode by using the voltage at the upper electrode as a reference.
First, at Step ST100 first data is written. Thereafter, first data is read, and second data of an opposite polarity is written and read. The first data is called the same state (SS) and the second data is called an opposite polarity state (OS).
As shown in the left area of FIG. 8C, a pulse voltage Vp of the positive polarity is applied to the capacitors Cx and Cy to make the capacitors have “0” polarized states. Next, a pulse voltage of the positive polarity is applied to the capacitor Cx and a pulse voltage of the negative polarity is applied to the capacitor Cy to write “0” in the capacitor Cx and “1” in the capacitor Cy. The first data (SS) is therefore stored.
At the next Step ST110, the capacitors written with the first data (SS) are held in a heated state, e.g., 150° C. and for a long time, e.g., 10 hours. Deterioration of stored information is accelerated in the heated state. There is a possibility that a hysteresis shift occurs due to imprint. Thereafter, at Step ST120 the first data (SS) is read.
As shown in the left portion of the central area of FIG. 8C, a pulse voltage of the positive polarity is applied to the capacitors. As the pulse voltage rises, positive charges U corresponding to “0” are drained out from the capacitor Cx to the bit line BL and positive charges P corresponding to “1” are drained out from the capacitor Cy to the bit line /BL. The stored first data (SS) is read from a difference between the positive charges. Since the stored information is lost by the read operation, in accordance with the read information, “0” is written again in the capacitor Cx and “1” is written again in the capacitor Cy. If polarization is degraded, the first data may not be read in some cases. It is possible to inspect the retention characteristics by reading the first data (SS).
At Step ST130, the second data (OS) of opposite polarities is written. As shown in the right portion of the central area of FIG. 8C, a pulse voltage Vp of the positive polarity is applied to the capacitors to make the capacitors have “0” polarized states. Next, a pulse voltage Vn of the negative polarity is applied to the capacitor Cx to write “1” and a pulse voltage Vp of the positive polarity is applied to the capacitor Cy to write “0”. If there is imprint, stored polarization reduces.
At Step ST140, the written second data is held for a short time, e.g., 5 seconds. This realizes relaxation and stabilized temperature and functions to prevent imprint evaluation from becoming rough.
At the next Step ST150, the second data (OS) is read. As shown in the right area of FIG. 8C, a pulse voltage of the positive polarity is applied to the capacitors. As the pulse voltage rises, positive charges P corresponding to “1” are drained out from the capacitor Cx to the bit line BL and positive charges U corresponding to “0” are drained out from the capacitor Cy to the bit line /BL. The stored second data (OS) is read from a difference between the positive charges. Since the stored information is lost by the read operation, in accordance with the read information, “1” is written again in the capacitor Cx and “0” is written again in the capacitor Cy.
If a polarization amount reduces due to imprint of the first data, the second data may not be read in some cases. It is possible to inspect the imprint characteristics by reading the second data (OS). If life evaluation is to be performed, the flow returns to Step ST100 from Step ST150 and the inspection Steps are repeated.
In actual inspection of FeRAM, device inspection and monitor inspection are performed. The former performs defect inspection for all memory cells, and the latter measures charge amounts read from selected memory cells.
FIG. 9A is a table showing the conditions of both the device inspection and monitor inspection. Voltages, temperatures and times used in the device inspection and monitor inspection are shown at each Step. The voltage of the device inspection is a minimum voltage in an operation voltage range at all Steps. This is because strict judgement is required by setting the conditions severe. The temperatures is 150° C. at the heated-shelf-aging Step ST110, and a high (H) temperature at other Steps. The shelf-aging time is 10 hours at the heated-shelf-aging Step ST110, and 5 seconds at Step ST140. The voltage of the monitor inspection is a central voltage in the operation voltage range. The temperature is 150° C. at the heated-shelf-aging Step ST110, and a room temperature (RT) at other Steps. The shelf-aging time is 10 hours at the heated-shelf-aging Step ST110, and 30 seconds at ST140. The voltage and temperature are constant at data read/write Steps of both the device inspection and monitor inspection.
The structure and manufacture method for FeRAM are disclosed, for example, in U.S. Pat. No. 5,953,619 which is incorporated herein by reference. An inspection method for FeRAM is disclosed, for example, in U.S. Pat. No. 6,008,659 which is incorporated herein by reference.
Inspection of FeRAM imprint poses a particular issue. JPA-2001-67896 proposes inspecting how imprint occurs by measuring a difference between operation lower limit voltages of opposite polarity data before and after high temperature shelf-aging. JP-A-2002-8397 proposes writing first data at a highest operation voltage (in the embodiment, writing first data a plurality of times until predetermined imprint occurs) to form imprint, thereafter writing opposite polarity second data, performing shelf-aging and reading, to realize inspection reflecting the imprint.